As spotted by patent sleuth @Underfox3, AMD has field a patent what appears to be a means of using a big.LITTLE-esque hybrid computing architecture that comes with a mixture of high-performance cores and smaller low-performance cores. As with all patent filings, this doesn't assure that AMD will bring this type of device to market, but it certainly shows the company is busy researching hybrid architectures.
The patent outlines a new instruction set subset implementation for low power operation. AMD's implementation allows for one subset of instructions to execute on larger full-featured processing cores optimized for higher performance, while a second subset of instruction run on smaller simplified cores designed for power efficiency. AMD's patent outlines a method whereby the cores use a shared memory location to enable threads to move between the two types of cores based upon certain variables.
In practice, the big cores would execute heavy performance-sensitive workloads, while the smaller cores would execute light tasks. When a core isn't busy, it could be shut off, thus improving power consumption further.
Intel has already forged ahead with a hybrid design with its Lakefield chips (half-heartedly branded as Big-Bigger), but unlocking maximum efficiency requires the operating system and applications to be aware of the architecture so they can target threads to the correct cores. There's already plenty of work underway to support that technique.
The method described in AMD's patent appears to allow the processor to independently sort out which type of thread should run on each cluster based on the instructions supported by the cores, with each type of core supporting either all instructions or a reduced subset. The processor could also shift threads between the cores based on utilization. For example, if the large core is underutilized, the processor would shift the thread to the small core (provided it supports the instructions). If the small core is over-utilized, the thread would shift to the larger core.
The approach appears to reduce or negate the need for OS intervention, which could lead to broader adoption of hybrid computing devices. The patent also explains an example wherein the clusters of cores could be CPUs, GPUs, or DSPs, meaning there's a dizzying array of possible combinations.
Intel uses multiple stacked dies that it ties together with its Foveros 3D stacking die-to-die interface, but that type of advanced packaging tech isn't necessarily required for this type of design. If AMD releases a hybrid computing design, it could come as one large die or an MCM design that leverages many of the fundamental concepts behind its existing architectures, among other possibilities.
However, as with all patents, AMD's filing doesn't guarantee that we will see new products based on the design. Underfox also cautions that the patent is still in the adjustment phase, so it is subject to change. Regardless, the filing certainly shows that AMD is actively researching its own type of hybrid implementations.
The Link LonkAugust 09, 2020 at 05:09AM
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AMD Files Patent for big.LITTLE-esque Hybrid Computing Implementation - Tom's Hardware
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