At Architecture Day 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making on its six pillars of technology innovation: process and packaging, architecture, memory, interconnects, security and software. Intel is taking full advantage of its unique position to deliver a mix of scalar, vector, matrix and spatial architectures deployed in CPUs, GPUs, accelerators and FPGAs – unified by oneAPI, an industry-standard open programming model to simplify application development.
Intel revealed its 10nm SuperFin technology, representing the largest single intranode enhancement in the company’s history and delivering performance improvement comparable to a full-node transition. Intel also unveiled architectural details of its Willow Cove microarchitecture and the Tiger Lake system-on-chip architecture for mobile client and provided first looks at its fully scalable Xe graphics architectures. Together with Intel’s disaggregated design approach and coupled with advanced packaging technology, XPU offerings and software-centric strategy, the company is focused on developing leading products across its portfolio to customers.
10nm SuperFin technology combines Intel's enhanced FinFET transistors with a Super MIM capacitor and an improved interconnect metal stack to deliver performance improvements comparable to a full-node transition, representing the largest single, intranode enhancement in Intel’s history. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
10nm SuperFin technology combines Intel's enhanced FinFET transistors with a Super MIM capacitor and an improved interconnect metal stack to deliver performance improvements comparable to a full-node transition, representing the largest single, intranode enhancement in Intel’s history. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
10nm SuperFin technology combines Intel's enhanced FinFET transistors with a Super MIM capacitor and an improved interconnect metal stack to deliver performance improvements comparable to a full-node transition, representing the largest single, intranode enhancement in Intel’s history. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
10nm SuperFin technology delivers a process performance boost that makes it the largest single, intranode enhancement in Intel's history, essentially the same level of performance achieved over multiple steps at 14nm and nearly the equivalent performance of a full-node transition. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
10nm SuperFin technology combines an enhanced FinFET transistor, improved interconnect metal stack and new Super MIM capacitor to achieve a performance boost that makes it the largest single intranode enhancement in Intel's history. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
The Tiger Lake mobile client architecture, built using Intel 10nm SuperFin technology, achieves a greater than generational performance increase in both its CPU and graphics and adds a number of new features -- all while increasing power efficiency. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
The Tiger Lake mobile client architecture, built using Intel 10nm SuperFin technology, includes Willow Cove CPU cores, the first ever Xe architecture graphics, new AI capabilities, rich input/output and more. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel's advanced packaging roadmap is built on decades of research and development, leading to new innovations in multiple dimensions and enabling new chip designs with lower cost, greater flexibility and quicker time to market. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel's CPU core roadmap now includes a new Alder Lake performance hybrid architecture that will combine Golden Cove and Gracemont cores in one highly efficient product arriving in 2021. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
The Willow Cove CPU core builds on the Sunny Cove foundation and employs 10nm SuperFin technology to achieve a dramatic frequency increase, while adding a redesigned cache architecture and control flow enforcement technology for security. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
The Willow Cove CPU core in Tiger Lake is faster and more efficient than its predecessor, enabling generational CPU gains in power-limited performance and in unconstrained performance across the board. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Xe-LP is Intel’s most efficient architecture for PC and mobile computing platforms with up to 96 EUs, and comes with new architecture designs including asynchronous compute to deliver greater dynamic range and frequency uplift. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Xe-HP is the industry’s first multitiled, highly scalable, high-performance architecture, providing data center-class, rack-level media performance, GPU scalability and AI optimization. It covers a dynamic range of compute from one tile to two and four tiles, functioning like a multicore GPU. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel's GPU strategy is rooted in Xe, a single architecture that can scale from teraflops to petaflops. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Designed with software first, scalability next and optimized for exciting new workloads, a full range of Intel Xe GPUs will be released. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel provides memory and storage options ranging from microseconds to nanoseconds of latency to solve for challenges between levels of the memory and storage hierarchy and enable better, faster access to all of the data a company must analyze. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Looking ahead to its Gold release of oneAPI, Intel will provide developers with a solution that has “production quality and performance” across scalar, vector, matrix and spatial architectures. oneAPI Gold will be available to developers later this year. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel's vision for the future of security will protect the computational and data execution perimeter in a future characterized by billions of interconnected devices executing across four architectures, through six or more levels of memory and through another four to six layers of interconnect. At Architecture Day in August 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
Intel Chief Architect Raja Koduri holds up Intel's Xe-HP single-title form factor, the industry’s first multitiled, highly scalable, high-performance architecture, providing data center-class, rack-level media performance, GPU scalability and AI optimization. At Architecture Day in August 2020, Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
During Intel Architecture Day, Chief Architect Raja Koduri introduces the SuperFin generation of transistors, combining the advantages of the SuperMIM capacitor innovation and FinFet enhancements to deliver Intel's largest single, intranode enhancement in its history. At Architecture Day in August 2020, Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
During Intel Architecture Day 2020, Chief Architect Raja Koduri spotlights progress in transistor-resilient design, focus on XPU architectures and an emphasis on a software-first approach to hardware design. At Architecture Day in August 2020, Koduri, Intel fellows and architects provided details on the progress Intel is making. (Credit: Intel Corporation)
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